1. Field of the Invention
The present invention relates to direct memory access (DMA) computer systems. More particularly, the invention relates to a DMA computer system for driving an LCD display in a GPS receiver.
2. Description of the Prior Art
DMA controllers are frequently used in computer systems for transferring blocks of data between the computer system""s main memory and a peripheral device without burdening the computer system""s CPU. DMA controllers are advantageous because they allow the CPU to continue executing other programs and control functions while the DMA controller drives the peripheral device.
In conventional DMA computer systems, the DMA controller takes control of the address, control, and data buses of the computer system when transferring data to a peripheral device. This can slow the CPU because the DMA controller competes with the CPU for instruction fetches and memory access. This problem is commonly referred to as xe2x80x9ccycle stealing.xe2x80x9d
Cycle stealing is particularly a problem in computer systems that use DMA controllers to drive peripherals that require a high average data rate. For example, in GPS receivers, DMA controllers are commonly used to drive LCD displays. LCD displays used in newer GPS receivers are larger and require a higher refresh rate, thus requiring their DMA controllers to steal more CPU cycles.
Solutions to cycle stealing, such as using dual-port RAMs or dedicated LCD controllers with internal memory for use as refresh buffers, have been developed. However, these solutions require relatively complex and expensive circuitry and/or memory devices and are therefore less desirable for many applications such as relatively low-cost GPS receivers.
The present invention solves the above-described problems and provides a distinct advance in the art of DMA computer systems. More particularly, the present invention provides a DMA computer system for driving a peripheral device such as an LCD display of a GPS receiver without stealing excessive cycles from the CPU and therefore overly slowing the CPU. The present invention also provides such a DMA control system that is relatively simple and economical to manufacture particularly when the memory for the DMA is integrated with the CPU and DMA controller and therefore suitable for many applications.
The DMA computer system of the present invention broadly includes a CPU, a first memory that may be written to or read by the CPU, a second memory that may be written to or read by the CPU, and a DMA controller coupled with the CPU and the second memory. The DMA controller is operable to: read data from the second memory and transfer the data to the peripheral device; delay the CPU from accessing the second memory while the DMA controller is reading data from the second memory; enable the CPU to regain access to the second memory once the DMA controller has finished reading data from the second memory; and allow the CPU to access the first memory without delay even while the DMA controller is reading data from the second memory.
One preferred application of the DMA computer system is for driving and/or refreshing an LCD display of a GPS receiver. Much of the data that the CPU requires for normal operation of the computer system and most of the instruction fetches are stored in the first memory. Data necessary to drive and/or refresh the display is stored in the second memory. To drive and/or refresh the display, the DMA controller transfers data from the second memory to the LCD display and temporarily delays the CPU any access to the second memory by suppressing the clock of the CPU until the DMA cycle is completed. During a DMA read, the CPU may continue operating in a normal fashion and may retrieve data and instructions from the first memory without delay.
These and other important aspects of the present invention are described more fully in the detailed description below.